Formation of through-silicon via (tsv) in silicon substrate

ABSTRACT

To form a through-silicon via (TSV) in a silicon substrate without using plating equipment or using sputtering equipment or small metal particles, and form an interlayer connection by stacking a plurality of such silicon substrates, a through hole of a silicon substrate is filled using molten solder itself. In detail, solid solder placed above the through hole of the silicon substrate is molten and the molten solder is guided to and filled in the internal space. A metal layer can be deposited on an internal surface of the through hole beforehand, and also an intermetallic compound (IMC) can be formed in a portion other than the metal layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 from JapanesePatent Application No. 2011-107280 filed May 12, 2011, the entirecontents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for forming a through-siliconvia (TSV) in a through hole of a silicon substrate in a 3D integrationtechnique, and more specifically relates to a technique of filling aninternal space of a through hole of a small diameter provided in asilicon substrate with molten solder. The present invention also relatesto an interlayer connection technique whereby a plurality of siliconsubstrates are stacked and joined to each other.

2. Description of Related Art

A through-silicon via (TSV) technique is one of the 3D integrationtechniques. An optimal fabrication method and material need to beselected for the TSV, according to specifications, architecture, silicon(substrate) thickness, and overall fabrication process of a product thatrequires this integration technique. A “through hole” filled with aconductive material becomes wiring that functions as a conductive pathafter the filling, and is also referred to as a “via”.

In a commonly known TSV fabrication method, a TSV is fabricated in asequence of (1) etching silicon (substrate) to form a through hole inthe silicon substrate, (2) forming an insulation film on an internalsurface of the through hole, and (3) filling a remaining internal spaceof the through hole with a conductive material.

As a conventional technique for (3) in this sequence of the fabricationmethod, a process of filling with the conductive material (e.g. Cu) byplating is known. However, not only this process requires dedicatedplating equipment, but also depositing the metal on the surface byplating takes time. Hence, this process has low yields.

FIG. 6 shows an example of a plating process in the conventionaltechnique

FIG. 6( a) shows an example of plating equipment in the conventionaltechnique. An object to be plated is placed at a position of a samplebetween a cathode and an anode. A plating solution contains ions ofmetal for plating.

FIG. 6( b) shows a situation where a void occurs in the through hole ofthe silicon substrate in the conventional technique. When there is sucha portion that is not filled with the conductive material, the functionas the conductive path cannot be sufficiently achieved. Even though theTSV conducts immediately after fabrication, there is a possibility thata conduction failure occurs as a result of deterioration with age. Thus,the conventional technique lacks reliability.

FIG. 6( c) shows a situation where the plating is not deposited (notdistributed) throughout the internal space of the through hole. This isprobably because, in the plating process, the metal ions contained inthe solution are grown and deposited with time, and so there is atendency that the metal deposits near an entrance between the internalspace and an external space of the through hole before it reaches theinternal space. In the experimental example shown in FIG. 6( c), adiameter of the through hole is φ=50 μm, and a depth of the through hole(a thickness of the silicon substrate) is t=400 μm. Under conditions ofsmaller scales than this, a further technique is needed to prevent sucha situation.

Patent Document 1 discloses a technique of small metal particles havinga nanocomposite structure. Such a technique can be applied to distributemetal particles of a small diameter throughout a through hole of a smalldiameter to thereby form a TSV. However, even if the metal particles canbe supplied in a closest packing manner, still it does not mean that themetal particles are supplied as a gap-free continuous body. Therefore,perfect filling cannot be ensured. FIG. 7 is a diagram for describingsuch a conventional technique that uses small metal particles.

Patent Document 2 discloses a technique whereby, for an insulationsubstrate made of a thermoplastic resin, a semi-molten metal mixture isformed by mixing a binder resin in metal particles, to improveinterlayer connection reliability of a multilayer substrate. However,required specifications and architecture are different between theinsulation substrate and the silicon substrate, and the diameter of thethrough hole relating to the present invention is of a much smallerorder than the diameter of the via hole (through hole) in PatentDocument 2.

Although the binder resin is mixed in expectation of its gap reductioneffect, the use of the binder resin causes generation of gas duringmelting and so rather raises a possibility of a void occurrence.

SUMMARY OF THE INVENTION

One aspect of the present invention provides a method of forming athrough-silicon via (TSV) in a through hole of a silicon substrate, themethod including: blocking a lower end of the through hole of thesilicon substrate, thereby keeping gas from flowing from the lower endof the through hole into an internal space of the through hole; placingsolid solder above the through hole of the silicon substrate forsubsequently filling in the through hole; evacuating a space thatincludes both the internal space and an external space of the throughhole; melting the placed solid solder to block an upper end of thethrough hole of the silicon substrate by the molten solder, therebykeeping gas from flowing from the upper end of the through hole into theinternal space of the through hole; and changing an evacuated state backto a previous state to cause a pressure difference between the externalspace and the internal space of the through hole so that the moltensolder is guided to the internal space of the through hole and theinternal space of the through hole is filled with the molten solder.

Another aspect of the present invention provides a silicon substrate inwhich a through-silicon via (TSV) is formed in a through hole by themethod of forming a through-silicon via (TSV) as described above.

Another aspect of the present invention provides a method of joining aplurality of silicon substrates which are each the silicon substratedescribed above, the method further including: providing a plurality ofsolder bumps on a first silicon substrate; providing a second siliconsubstrate on the plurality of solder bumps; and melting the solder bumpsby generating a specific temperature higher than a melting temperatureof the placed solid solder. Also provided is a 3D chip where the chipincludes a plurality of silicon substrates joined by this method.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention and its preferred embodiments, additional objects,features and advantages will be better understood by referring to thedetailed description of the exemplary embodiments when read inconjunction with the attached drawings, in which:

FIG. 1 illustrates a section diagram showing a 3D chips in which aplurality of silicon substrates are joined to each other according to anembodiment of the present invention.

FIG. 2 illustrates a schematic diagram showing a method for forming athrough-silicon via (TSV) in a through hole of a silicon substrate usingmolten solder itself, according to an embodiment of the presentinvention.

FIG. 3 illustrates a diagram for describing a structure in which a metallayer is deposited on an internal surface of the through hole of thesilicon substrate and a structure in which an intermetallic compound(IMC) is formed in a portion other than the metal layer, according anembodiment of the present invention.

FIG. 4 illustrates a diagram for describing a skin effect of the metallayer according to an embodiment of the present invention.

FIG. 5 illustrates a conceptual diagram for describing a process ofadding a fine powder of metal (Cu) into the through hole according to anembodiment of the present invention.

FIG. 6 illustrates a diagram showing an example of a plating process ina conventional technique according to an embodiment of the presentinvention.

FIG. 7 illustrates a diagram for describing a conventional techniquethat uses small metal particles according to an embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention has an object of forming a through-silicon via(TSV) in a silicon substrate without using plating equipment or smallmetal particles, and forming an interlayer connection by stacking andjoining a plurality of such silicon substrates.

In one aspect of the present invention, a through hole of a siliconsubstrate is filled using molten solder itself. In more detail, a lowerend of the through hole of the silicon substrate is blocked, solidsolder placed above the through hole (directly above or above and to theside of the through hole) of the silicon substrate is molten, and themolten solder is guided to and filled in the internal space of thethrough hole by a pressure difference between the external space and theinternal space of the through hole.

A through-silicon via (TSV) that has no conduction failure caused by avoid occurrence can be formed without a time-consuming process ofdepositing metal on an internal surface of a through hole by plating.

The metal layer deposited beforehand contributes to improved wettabilityof the internal surface of the through hole, which facilitates passageof a high frequency signal.

By forming the intermetallic compound (IMC) so as to prevent remeltingin a subsequent process, a high resistance to electromigration can beattained.

FIG. 1 illustrates a section diagram showing a 3D stacked body in whicha plurality of silicon substrates are joined to each other.

In this specification, the term “silicon substrate” has a broad conceptincluding a silicon interposer and a silicon chip typically with asubstrate shape so long as a through-silicon via (TSV) can be formed.The silicon chip is usually much thinner than the silicon interposer.

The plurality of silicon substrates are electrically and mechanicallyjoined through fine-pitch solder bumps. The solder bumps solidified as aresult of melting are shown in the drawing. The plurality of siliconsubstrates are joined by a process of providing a first siliconsubstrate, providing a plurality of solder bumps on the first siliconsubstrate, providing a second silicon substrate on the plurality ofsolder bumps, and melting the placed solid solder.

In the case where a required series of fabrication process (overallfabrication process) is such a type that stacks silicon substrates oneby one in a laminated structure, it is preferable to prevent remeltingeven when a specific temperature equal to or higher than a temperaturegenerated in a previous process to melt solid solder is generated in asubsequent process. This is because there is a possibility thatremelting causes an already joined silicon substrate situated below tobe displaced. A structure having such a resistance is referred to as astructure highly resistant to electromigration.

A metal layer can be deposited on an internal surface of the throughhole beforehand, and also an intermetallic compound (IMC) can be formedin a portion other than the metal layer.

FIG. 2 is a schematic diagram showing a method for forming athrough-silicon via (TSV) in a through hole of a silicon substrate usingmolten solder itself, according to an embodiment of the presentinvention.

First, a lower end of each through hole of the silicon substrate isblocked, as shown in FIG. 2( a). The blocking can be made with a moltensolder bump or an I/O pad shown in FIG. 1, as long as gas is kept fromflowing from the lower end of the through hole into its internal space.

In addition, sold solder prepared for subsequently filling the throughhole is placed above the through hole (directly above or above and tothe side of the through hole) of the silicon substrate, as shown in FIG.2( a). The solid solder can be platelike or spherical in shape.

In this state, a space including both the internal space and theexternal space of the through hole is evacuated, as shown in FIG. 2( a).There is no need to fear that the internal space of the through hole cannot be evacuated when the solid solder lies directly above the throughhole, because the actual solid solder has innumerable projections anddepressions on its surface and so there is a clearance between theinternal space and the external space of the through hole.

Various techniques for evacuating both the internal space and theexternal space of the through hole can be conceivable by a personskilled in the art. The term “evacuation” should be broadly interpretedso long as it is a process of causing a pressure difference between theexternal space and the internal space of the through hole.

Next, the solder is molten in the state where the space is evacuated, asshown in FIG. 2( b). For example, heating is performed at 260° C. orhigher, which is a melting point of solid solder (the melting point canbe 300° C. or higher depending on solder composition). The heatingmethod can be a method for heating the entire atmosphere or a method forheating only the solid solder (as intensively as technically possible).As a result, the placed solid solder melts and flows as a gap-freecontinuous body, so that the upper end of the through hole of thesilicon substrate is blocked by the molten solder. This keeps gas fromflowing from the upper end of the through hole into the internal space.

Lastly, the evacuated state is changed back to the previous state (i.e.FIG. 2( a)), as shown in FIG. 2( c). In other words, the vacuum isreleased. As a result, the external space of the through hole is broughtback to the same ambient pressure as in the previous state, causing apressure difference between the external space and the internal space ofthe through hole. Due to this pressure difference, the molten solder,flowing as a gap-free continuous body, is guided to the internal spaceof the through hole. Thus, the internal space of the through hole isfilled with the molten solder.

FIG. 3 is a diagram for describing a structure in which a metal layer isdeposited on an internal surface of the through hole of the siliconsubstrate and a structure in which an intermetallic compound (IMC) isformed in a portion other than the metal layer, according to the presentinvention.

FIG. 3( a) schematically shows a process of forming the intermetalliccompound (IMC) in the internal space of the through hole.

First, in FIG. 3( a 1), the metal layer is deposited on the internalsurface of the through hole. The deposition method can be plating (ofthe conventional technique shown in FIG. 6) or the like. A thin film ofgold (Au), for example, is a favorable material when wettability(affinity with other metal) in the next process and the like are takeninto consideration. A thin film of copper (Cu) is also applicable.

Next, in FIG. 3( a 2), a different kind of metal (e.g. solder) is filledin the portion other than the metal layer deposited on the internalsurface of the through hole. In FIG. 3( a 3), the intermetallic compound(IMC) is formed in the internal space of the through hole.

FIG. 3( b) is a diagram showing a distribution of the intermetalliccompound (IMC) formed in the case where Cu is used in the metal layerand solder (whose composition has Cu and Sn as main components) is usedin the other portion. A pure metal layer is formed at Pt1, while solderof Cu and Sn is filled at Pt2 in the other portion, creating a boundary.

Moreover, a metal composition of Ni and Au is contained further insideat Pt3 and Pt4. This is probably because, in the process where the solidsolder placed above the through hole (directly above or above and to theside of the through hole) of the silicon substrate is molten and guidedto the internal space of the through hole so as to be filled in thethrough hole as shown in FIG. 2, wiring metal and the like mounted abovethe through hole (directly above or above and to the side of the throughhole) of the silicon substrate diffuse into the solder.

FIG. 3( c) is a Cu—Sn system phase diagram showing a change in meltingpoint of the intermetallic compound (IMC). It can be expected that aphase according to this equilibrium state appears as long as Cu and Snare the main components of the composition. In two phases of compositionratio at two positions indicated by arrows, the intermetallic compound(IMC) with an increased melting point is formed to thereby preventremelting in a subsequent process.

In the experimental condition in FIG. 3( b), the through hole is 5 μm orless in diameter. This demonstrates that the present invention isapplicable even in such a case. The method for the present inventionseems to be more advantageous when the diameter of the through hole issmaller.

FIG. 4 is a diagram for describing a skin effect of the metal layeraccording to the present invention.

A cross section of the through-silicon via (TSV) (as viewed from abovein FIGS. 1 to 3) is schematically shown in FIG. 4. A pure metal layer isformed in a thickness portion close to the internal surface of thethrough hole (the periphery of the through hole), while an intermetalliccompound (IMC) state (or a similar state) is formed in a portion otherthan the metal layer. It is commonly known that an intermetalliccompound (IMC) has lower electric conductivity than pure metal.

On the other hand, metal having favorable electric conductivity isscarce in many cases, and Au, for example, is expensive metal. In viewof this, it is important to take a skin depth where a skin effectappears, into consideration. Throughout the filled internal space of thethrough hole, substantial electric conduction occurs only in thisthickness. Based on such an aspect, an appropriate thickness of themetal layer to be deposited beforehand can be determined. Thiseliminates waste of using redundant material, exceeding the requiredproduct specifications and architecture (overdesigned).

It is known that the skin depth by the skin effect is smaller when thefrequency is higher. In copper, silver, gold, and aluminum which aretypical materials having favorable electric conductivity, the skin depthis in a range of 0.64 μm to 0.84 μm when the frequency is as high as 10GHz.

FIG. 5 is a conceptual diagram for describing a process of adding a finepowder of metal (Cu) into the through hole. This process is effective inthe case of forming the intermetallic compound (IMC) as widely andreliably as possible. In the case where the metal layer depositedbeforehand is made of Cu and is thick, for example, in a range of 1 μmto 9 μm, Cu can be effectively mixed in the through hole.

By adding the fine powder of metal (Cu) into the internal space of thethrough hole before the solder melting process, it can be expected thatthe intermetallic compound (IMC) is effectively formed especially by asynergic effect that the fine powder and the metal layer are made of thesame metal (e.g. Cu), since the metal layer deposited beforehand isthick. The small metal particles in the conventional technique shown inFIG. 7 can be used in such a manner.

1. A method of forming a through-silicon via (TSV) in a through hole ofa silicon substrate, the method comprising: blocking a lower end of thethrough hole of the silicon substrate, thereby keeping gas from flowingfrom the lower end of the through hole into an internal space of thethrough hole; placing solid solder above the through hole of the siliconsubstrate for subsequently filling in the through hole; evacuating aspace that includes both the internal space and an external space of thethrough hole; melting the placed solid solder to block an upper end ofthe through hole of the silicon substrate by the molten solder, therebykeeping gas from flowing from the upper end of the through hole into theinternal space of the through hole; and changing an evacuated state backto a previous state to cause a pressure difference between the externalspace and the internal space of the through hole so that the moltensolder is guided to the internal space of the through hole and theinternal space of the through hole is filled with the molten solder. 2.The method according to claim 1, further comprising: depositing a metallayer on an internal surface of the through hole.
 3. The method of claim2, wherein the metal layer is a thin film of Au.
 4. The method of claim2, wherein the metal layer is a thin film of Cu.
 5. The method accordingto claim 2, wherein a thickness of the metal layer that is deposited onthe internal surface of the through hole is a specified thickness atwhich substantial electric conduction occurs.
 6. The method according toclaim 5, wherein the thickness of the metal layer is in a range of 0.64μm to 0.84 μm, and ranges therebetween, a diameter of the through holeis 50 μm or less, and a depth of the through hole is 400 μm or less. 7.The method according to claim 2, further comprising: forming anintermetallic compound (IMC) in a portion other than the metal layer inthe filled internal space of the through hole.
 8. The method accordingto claim 7, further comprising: adding a fine powder of metal which isCu into the through hole before the step of melting.
 9. The methodaccording to claim 8, wherein the metal layer has a thickness in a rangeof 1 μm to 9 μm, and ranges therebetween. 8-10. (canceled)
 11. A methodof joining a plurality of silicon substrates which are each the siliconsubstrate according to claim 8, the method comprising: providing aplurality of solder bumps on a first silicon substrate; providing asecond silicon substrate on the plurality of solder bumps; and meltingthe solder bumps by generating a specific temperature higher than amelting temperature of the placed solid solder.